1. Field of the Invention
The present invention generally relates to liquid crystal display devices, and more particularly to a liquid crystal display device capable of extending an arbitrary portion of a display at an arbitrary magnification. More particularly, the present invention is concerned with a liquid crystal display device equipped with an active-matrix type liquid crystal display panel having switching elements, such as TFTs (Thin Film Transistors), provided for respective pixels and arranged in a matrix formation, or a matrix type liquid crystal display panel having a matrix electrode structure called CS-ON-GATE. Further, the present invention relates to a display method of such liquid crystal display devices.
Recently, image signals output by a computer, a workstation or the like have been required to realize highly precise, high-quality display. Hence, there has been considerable activity in the development of a highly precise, high-quality display device. A display device of a matrix-formation structure is required to have a larger number of pixels (display elements). Further, it is required that a display device can operate in a plurality of display modes because a personal computer, a workstation or the like can output image signals in conformity with a plurality of display modes such as VGA, SVGA and XGA.
Generally, the image signals output by the computers have a predetermined number of pixels. For example, the VGA consists of 640.times.480 pixels, the SVGA consists of 800.times.600 pixels, and the XGA consists of 1024.times.768 pixels.
When an image formed in the VGA or SVGA mode is displayed on a display device capable of operating in the XGA mode, such an image is partially displayed on the whole display screen. In this case, the operator will feel that the display is not bright. Such feeling is particularly conspicuous in the display device of a projection type. In order to avoid the above problem, the original image is enlarged and displayed so that an extended image is displayed on the substantially whole display screen.
Normally, a display is enlarged in both the horizontal and vertical directions. In the following, an enlargement in the horizontal direction will be described first with reference to FIGS. 1 through 4, and an enlargement in the vertical direction will be described second.
2. Description of the Related Art
FIG. 1 is a block diagram of a liquid crystal display device related to the present invention. A liquid crystal display device 9 shown in FIG. 1 includes a liquid crystal display panel 1A, a horizontal driver circuit 3, a vertical driver circuit 2, and a timing control circuit 4. The liquid crystal display panel 1A has switching elements provided for respective pixels and arranged in a matrix formation. Such switching elements are formed of, for example, thin film transistors. The horizontal driver circuit 3 performs a horizontal scan control in which image data amounting to one horizontal line (which is also called scan bus line) is serially written into the switching elements equal to one horizontal line in synchronism with a shift clock signal for the horizontal direction. The above horizontal scan control is initiated in a start signal for the horizontal scan. The vertical driver circuit 2 performs a write timing control in which the switching elements forming one vertical line (which is also called data bus line) are serially selected in synchronism with a shift clock signal for the vertical direction. The above write timing control is initiated in response to a start signal for the vertical scan. The timing control circuit 4 generates timing control signals 4a for controlling a displaying operation. The timing control signals 4a include the above-mentioned start signal for the horizontal scan, the timing signal for the horizontal direction, the start signal for the vertical scan, and the timing signal for the vertical direction.
An image memory 4A is provided in the timing control circuit 4 in order to display an image extended in the vertical direction. The same image data as that forming an image of one horizontal line is written, every predetermined number of horizontal lines dependent on an enlargement ratio, into the next line so that the identical image data is written into the two consecutive horizontal lines consisting of the last line of the predetermined number of horizontal lines and the above next line. Since the image data is serially applied to the horizontal driver circuit 3, there is not enough time to write identical image data into two consecutive horizontal lines. The image memory 4A is used to realize the above write operation. The image memory 4A may be formed of an FIFO (First-In First-Out) memory and adjusts the timing at which image data is received and the timing at which image data is written every line.
FIG. 2 is a timing chart of the timing control circuit 4 equipped with the FIFO memory 4A. As shown in FIG. 2, the same image data as that forming the last line of three horizontal lines is written, every three horizontal lines, into the next horizontal line following the above last horizontal line. Image data is serially written into the FIFO memory 4A every horizontal line. The read timing of the FIFO memory 4A is controlled so that image data forming the last line of the three horizontal lines is read again to form the image of the next horizontal line. For example, image data (3) equal to one line is consecutively read from the FIFO memory 4A twice and is applied to the horizontal driver circuit 3 shown in FIG. 1.
The liquid crystal display panel 1A shown in FIG. 1 can be replaced by a matrix-type liquid crystal panel 1B having a matrix electrode structure called CS-ON-GATE directed to a high aperture ratio.
FIG. 3 is an enlarged plan view of a pixel and its peripheral circuit of the matrix type liquid crystal panel 1B of the CS-ON-GATE matrix electrode structure. FIG. 4 is a circuit diagram of the structure shown in FIG. 3. As is known, the CS-ON-GATE matrix electrode structure has a TFT substrate on which data bus lines (signal electrodes) including a data bus line 5A and scan bus lines including scan bus lines 5B-1 and 5B-2 are formed in a matrix formation. At the crosspoints of the lines are provided switching elements 6 formed of TFT. A common electrode is provided on a common substrate. The data bus lines including the line 5A are connected to the horizontal scan driver 3 shown in FIG. 1, and the scan bus lines including the lines 5B-1 and 5B-2 are connected to the vertical driver circuit 2. A liquid crystal display capacitor CLC is connected between the TFT 6 and a common substrate reference voltage VC.
A compensation capacitor CS, provided for each pixel, is provided to minimize a drop of the pixel potential caused by a floating capacitance of the TFT 6. The compensation capacitor CS is connected to the TFT 6 and the scan bus line next to the scan bus line to which the above TFT 6 is connected. In the case of FIG. 4, the compensation capacitor CS is connected to the TFT 6 and the adjacent scan bus line 5B-2.
The voltage corresponding to the image data (one-pixel image data) is applied to the data bus line 5A by the horizontal driver circuit 3. When the scan bus line 5B-1 is selected by the vertical driver circuit 2, the above voltage of the data bus line 5A is applied to the display capacitor CLC via the TFT 6 and is held until the scan bus line 5B-1 is selected the next time. The applied voltage determines the orientation of the liquid crystal (pixel) and thus controls the optical transparency ratio. Hence, a gradation display can be realized.
The inventors consider that the related art which has been described with reference to FIGS. 1 and 2 has the following disadvantage. As has been described, it is necessary to provide the image memory 4A formed of an FIFO memory or the like in order to realize an enlarged display enlarged in the vertical direction. The use of the image memory 4A requires a complex read timing control in order to realize the above-mentioned enlarged display.
The inventors consider that the related art which has been described with reference to FIGS. 3 and 4 has the following disadvantage. The adjacent scan bus lines 5B-1 and 5B-2 are AC-coupled together via the compensation capacitor CS. Hence, it is very difficult to drive the AC-coupled adjacent scan bus lines and apply identical pixel data to the data bus line 5A. Hence, the enlargement control as shown in FIG. 2 cannot be applied to the CS-ON-GATE type liquid crystal display panel 1B. That is, identical image data cannot be applied to the two consecutive horizontal lines.
A general procedure for enlarging an image in the horizontal direction is as follows. Generally, the frequency of a sampling clock is made higher in order to obtain a larger number of samples. The sampling clock is extracted from the image signal by a PLL (Phase-Locked Loop) circuit. originally, the frequency of the sampling clock is selected so that the peaks of the image signal in analog formation are sampled. When the frequency of the sampling clock is increased, the image signals are sampled at portions other than the peaks. In this way, an increased number of samples necessary to enlarge the image in the horizontal direction can be obtained.
However, the samples obtained by sampling the image signal at portions other than the peaks will cause problems. For example, an interference fringe or flicker noise may appear on the displayed image.